1. Field of the Present Disclosure
The present disclosure relates to a semiconductor device and a fabricating method thereof, and more particularly, to a bipolar transistor and a fabricating method thereof.
2. Description of the Related Art
Technical developments in CMOS technology, i.e., technology where complementary n-channel and p-channel MOS transistors are formed on adjacent regions of a chip, has enabled the manufacturers of CMOS devices to create high-speed and high-density integrated circuits at low costs. Thus, CMOS devices have been used for a wide variety of applications, such as high frequency circuits and systems-on-chip. Although CMOS devices generally have superior operating characteristics compared to devices made using other technologies, CMOS is not a suitable technology to produce the low-noise circuitry necessary for certain high-frequency devices, such as low noise amplifiers (LNAs) or voltage controlled oscillators (VCOs).
In order to overcome these shortcomings, manufacturers have incorporated bipolar transistors on the same chip with CMOS transistors to create devices that perform dedicated circuit functions. In these mixed-technology chips, bipolar transistors are used for high frequency circuits while CMOS devices are used for logic circuits. This is because compared to the MOS field effect transistor the bipolar transistor has a lower noise characteristic, a wider linear gain range, a superior frequency response and a better current driving capability.
A bipolar transistor includes a base, an emitter and a collector. In the bipolar transistor, carriers move from the emitter to the collector by applying a forward bias between the emitter and the base and supplying a reverse bias between the base and the collector. Bipolar transistors can be classified as either a vertical bipolar transistor or a horizontal bipolar transistor according to the direction of carrier movement.
A vertical bipolar transistor has a stack structure made of a collector, a base and an emitter in sequence. A conventional vertical NPN bipolar transistor is formed by forming a P-type base region on an N-type emitter region, depositing an insulating layer, patterning the insulating layer to form an emitter window therein, and injecting an N-type impurity to the base region through the emitter window to form an emitter region. Unfortunately, it is very difficult to form a shallow emitter junction to a depth less than 300 nm through an ion implantation process. Nonetheless, such a shallow emitter junction depth is required to provide high operating speed.
In order to overcome the difficulty in forming shallow emitter junctions, a fabricating process was introduced that involves fabricating a vertical bipolar transistor by forming an un-doped polysilicon single layer after forming the emitter window, performing the ion implantation process to inject an N-type impurity into the un-doped polysilicon layer and performing a thermal process. For this bipolar transistor, the thickness of the emitter's un-doped polysilicon layer significantly affects the transistor's characteristics.
For transistors made according to this process, the un-doped polysilicon layer can be used as an emitter electrode after impurities are injected into the un-doped polysilicon layer and a thermal process is applied. In order to provide a low emitter electrode resistance, it might seem preferable to form the un-doped polysilicon layer to have a thick thickness. However, given that the junction depth profile of the emitter region is formed by diffusing an impurity into the base region through a thermal process, it might otherwise seem better to form the un-doped polysilicon to have a thin thickness. Such a manufacturing process is described below with reference to FIG. 1, which shows a cross-sectional view of a bipolar transistor formed while using a single polysilicon layer.
As shown in FIG. 1, the bipolar transistor includes a collector region 102, a device isolation layer 104, a base electrode 106, a base region 108, an insulating layer 110, a polysilicon emitter electrode 112 and an emitter region 114.
For a given emitter window width W1, the width W2 of the emitter region 114 decreases as a function of the thickness t of the polysilicon emitter electrode 112. That is, as the thickness t of the polysilicon emitter electrode 112 increases, width W2 will decrease. This is because impurities are not well diffused into edge portions of the emitter as compared to other portions. Accordingly, an impurity junction region 114S formed at the edge portions will have a different depth as compared to other portions of the emitter region 114. That is, for a given emitter window width W1, the width W3 of impurity junction region 114S increases in proportional to the thickness t of polysilicon emitter electrode 112 while the width W2 of emitter region 114 decreases.
In order to decrease resistance, the thickness t of polysilicon emitter electrode 112 must increase. However, an increase of the thickness t of the polysilicon emitter electrode 112 will cause the width W3 of impurity junction region 114s to increase and the width W2 of emitter region 114 to decrease proportionally. Unfortunately, variations in the width W3 of impurity junction region 114S and the width W2 of emitter region caused by standard variations in processing, such as width variations of the emitter window and thickness variations of the polysilicon emitter electrode, become greater in proportional to the width of polysilicon emitter electrode 114. Such variations degrades 1/f noise characteristics and gain deviation characteristics. It is expected that the 1/f noise characteristics and the gain deviation characteristics are closely related to the interface characteristics between the base region 108, the polysilicon emitter electrode 112 and any dangling bonds in the grain boundary of the polysilicon electrode. Dangling bonds affect the recombination of carriers moving from the base to the emitter and has a proportional relationship to base current. The 1/f noise is related to dangling bonds in proportional to a square of base current IB.
Unfortunately, the conventional bipolar transistor described above cannot simultaneously provide low emitter resistance, superior 1/f noise characteristics and the desired gain deviation characteristics. This is because the conventional method of forming the emitter electrode and the emitter region using a single polysilicon layer causes the resistance of the emitter electrode, the 1/f noise characteristics and the gain deviation characteristics have a trade-off relationship to one another.